Method for fabricating electrical connecting element, and electrical connecting element

ABSTRACT

The invention comprises a method for manufacturing electrical connecting elements or semifinished products. Microvias are formed in a dielectric substrate layer by piercing a substrate layer ( 1 ) through a first conducting layer ( 3 ), which essentially covers an entire side of the substrate. The perforation depth (d) is at least equal to the total thickness of the substrate and the first conducting layer. The conductor material of the first conducting layer ( 3 ) during the piercing step is deformed so that it partially covers the wall of the hole fabricated by the piercing process. The little remaining distance between the conductor material and the opposite side of the substrate layer can easily be bridged by plating the side of the first conducting layer with additional conductor material. In this way, a reliable via contact is formed.

[0001] The invention relates to methods for fabricating electricalconnecting elements such as Printed Circuit Boards (PCBs),High-Density-Interconnects (HDIs), Ball-Grid-Array—(BGA-) substrates,Chip Scale Packages (CSP), Multi-Chip-Module—(MCM) substrates, etc. Italso relates to a electrical connecting element and to an apparatus forfabricating electrical connecting elements.

[0002] In modern circuit board technology, due to increasingminiaturization, conventionally drilled through holes are more and morereplaced by microvias. Methods for fabricating such microvias includelaser drilling and plasma drilling as well as photochemical structuring.A new method for fabricating microvias has been disclosed in WO00/13062. This new technology approach, the Micro-Perforation, is amethod including mechanical embossing of micro-holes into deformabledielectric material. With Micro-Perforation, any shape of a microvia isfeasible. By controlling the length and size of perforation-tips alsothe formation of very small blind microvias can be achieved.

[0003] However, the fabrication of blind microvias by Micro-Perforationand the other state of the art methods have in common that a viafabricating step has to be followed by a contacting step between theconducting layers or pads across the via. Depending on the microviageometry, such a contacting step may be a chemical or physicaldeposition of some conductor material as a seed layer followed by anelectroplating step. Plating of very small blind holes of 100 μmDiameter and less is very tricky and often results in non-plated holesand consequently scrapped boards. Also, incomplete plating of side wallsof the holes affects the reliability of the boards.

[0004] If, according to the state of the art, a build-up of three, fouror more layers is produced, in a first step a core consisting of twoconducting and structured layers separated by a dielectric substratelayer with vias is provided. Then, dielectric layers which are on oneside coated by a metal layer are subsequently laminated on the core,perforated, plated, and structured. This procedure even enhances theimpact of the above mentioned shortcomings of the present laminationmethod. Testing of the via reliability and of the quality of thestructuring of the outermost layer is only possible after the latter hasbeen laminated to the core and structured. If a via side wall isincompletely plated, the entire board has to be scrapped, including apossibly perfect core.

[0005] It therefore would be desirable to have a method which makes thisplating step more reliable and leads to a reduction of production costand of environmental impact caused by wet chemical bathes. Preferably,the method should also make more efficient testing possible and preventthe situation that an entire board including perfect parts has to bescrapped.

[0006] It is therefore an object of the invention to provide a methodfor the fabrication of microvias which overcomes drawbacks of existingmethods and which especially makes the electroplating step for making anelectrical contact between two conducting layers more reliable andefficient.

[0007] This object is achieved by the method as defined in the claims.

[0008] According to the invention, microvias are formed in a dielectricsubstrate layer by piercing the substrate layer through a firstconducting layer, which essentially covers an entire side of thesubstrate. The perforation depth is at least equal to the totalthickness of the substrate and the first conducting layer. The conductormaterial of the first conducting layer during the piercing step isdeformed so that it partially covers the wall of the hole fabricated bythe piercing process. The little remaining distance between theconductor material and the opposite side of the substrate layer caneasily be bridged by plating the side of the first conducting layer withadditional conductor material. If, at the pierced spot, the substratelayer comprises a conductor covering, a reliable via contact is formed.If, however, it is free of conductor material, a protrusions at thepierced spots may result. These protrusions may be soldered or welded toconducting material of an other substrate with structured conductorlayers in order to manufacture a several-layer-build-up.

[0009] After the piercing step, a plasma or wet chemical cleaning stepmay follow to remove possible residues.

[0010] As already mentioned, after the piercing step, the distancebetween the deformed conductor material, e.g. copper, from the firstconductor layer to the second side of the substrate can easily bebridged by the plated conductor material. There is no need of having apre-covering of the surface by a chemical deposited copper. Thiseliminates all the critical plating processes which have usually to beperformed in order to prepare the surface of the dielectric material tocover it by a chemically deposited metal layer as a seed layer for theplating.

[0011] The invention also refers to a product produced by the abovemethod, namely to an electrical connecting element or to a semifinishedproduct.

[0012] In the following, examples of preferred embodiments of theinvention are described with reference to drawings. In the drawings,

[0013]FIGS. 1a through 1 e schematically show a PCB/HDI substrate (or acomponent of such a PCB/HDI substrate, respectively) during differentstages of the production,

[0014]FIGS. 2a through 2 e schematically represent a top cap or a bottomcap of a four layer build up PCB/HDI during different stages of theproduction, and

[0015]FIGS. 3a through 3 d schematically show the production of acomponent of a four layer build-up using components produced accordingto FIGS. 1a through 1 e and 2 a through 2 e.

[0016]FIGS. 1a through 1 e show a process to manufacture PCB/HDIsubstrates or semi-finished products for the production thereof by meansof a of micro-perforation technique. In the following, with reference toFIGS. 1a-1 e, 2 a-2 e and 3 a-3 d a process for manufacturing a fourlayer build-up is described. It should be noted, however, that thedescribed process can also be used to produce an electrical connectingelement of 2 layers, 3 layers 5 layers, 6 layers or any other number oflayers. A PCB/HDI substrate of two layers, for example, can be producedusing the procedure of FIGS. 1a-1 e. Also a product produced accordingto FIGS. 2a through 2 e may by itself serve as a two layer PCB/HDIsubstrate. In order to produce a PCB/HDI substrate of more layers, tosuch a substrate produced in accordance with FIGS. 1a through 1 e (assemifinished product), the appropriate number of semifinished productsproduced according to FIGS. 2a-2 e has to be added.

[0017] In FIG. 1a, the core base material 1, which is already coated bya first conducting layer 3 on its first side (or top side) and a secondconducting layer 5 on its second side (or bottom side), is shown. Thebase material (or substrate material) 1 is a dielectric, e.g. epoxy,polyimide, a liquid crystal polymer (LCP), polysulfone, polyester(PEEK), Polycarbonate etc. The conducting material may be copper or acopper alloy. It may also be an other conducting material such as silveror a silver alloy. In the following description of an example, it isassumed that the conducting layers are clad copper layers. As anexample, the thickness of the base material by be around 25-100 μm, thethickness of each clad copper layer around 5-35 μm. It however goeswithout saying that the invention also works for other materialthicknesses.

[0018] In this clad material, by a first Micro-Perforation (MP) stepmicrovias are formed: In FIG. 1b, a perforation tip 11 being appliedfrom the first side of the substrate layer 1 is shown schematically. Theperforation tip pierces the first conducting layer 3, the substratematerial 1 as well as, at least partially, the second conducting layer5. The perforation depth is denoted by d in the Figure. The perforationtip can be part of a sequentially working perforation tool, of aperforation die, a perforation reel, etc. Concerning different ways tomicro-perforate and appropriate tools, it is referred to the literature,especially to published patent applications of this applicant. Theperforation tool comprises also a support plate which is soft orflexible enough to allow the perforation tip to penetrate so deep thatit protrudes on the bottom side.

[0019] The Micro-Perforation (MP) process may e.g. be carried out atroom temperature. It may, depending on the type of the polymer layer,also be performed at a different temperature, e.g. at a temperaturebetween room temperature and 300° C. or 400° C. By pressing the tipsinto the material, the dielectric material is deformed and thrust aside.At the same time, the copper is deformed by the perforation tip. Afterthe perforation process, it covers an essential portion of the side wallof the hole formed by the MP process, as sketched in FIG. 1c.

[0020] The perforation step may be, depending on the materials involvedand the shape of the perforation tip, followed by a plasma or wetchemical cleaning step.

[0021] The product after the MP process is shown in FIG. 1c. The wallsof the hole fabricated by piercing are at least partially covered bycopper material of the top copper layer. Then, at least the first sideis plated (FIG. 1d). By this process, the remaining gap between the toplayer material and the bottom layer material is bridged and a via isformed.

[0022] It may be advantageous to plate both sides at once, as shown inthe figure. It should be emphasized, though, that only the plating ofthe side from which the holes have been applied is crucial. It couldwell be that the thickness of the second copper layer (and possibly evenits structure, see below) of the prefabricated product of FIG. 1a, hasbeen chosen so that it does not have to be treated further. By theplating process, the gap between the conductor material of the firstlayer ant the second layer is bridged and a connection is formed.

[0023] A following photo-patterning process of both copper layers (FIG.1e) may e.g. be carried out according to state-of-the-artphoto-patterning processes and is not further described here. Thesemifinished product resulting is denoted by 21 in the figure.

[0024] The top and the bottom cap layer are made in a way that isdifferent from the forming of the core. The copper layer 33, which isclad on one side of an uncured dielectric material 31 only, asrepresented in FIG. 2a, is perforated by the MP process analogously tothe core. The copper clad side of the dielectric material in thefollowing is called the top side, the opposing side will be named theback side. For the MP process, again a perforation tool 11 is used (FIG.2b).

[0025] In FIG. 2c, the material after the MP process is shown. Again,the walls or the hole are partially covered by copper.

[0026] After the plating step, as shown in FIG. 2d, the walls of thehole are entirely covered with copper so that a via is formed. Inaddition, some copper material protrudes on the bottom side.

[0027] As can be seen in FIG. 2e, these protrusions 35 are subsequentlytinned. This tinning can e.g. be done by pressing the cap layer on asoft and possibly warm solder material block or sheet. Some soldermaterial 37 then sticks to the protrusions 35.

[0028] The resulting product is denoted by 51 in the figure. After thisprocedure, a plasma cleaning step may be carried out on the back side ofthe product 51 in order to clean away possible pollutants and to removesome dielectric material around the copper protrusions. The product 51may serve as semifinished product for manufacturing aseveral-layer-build-up, e.g. as described below. As an alternative, theproduct 51 may also serve as a two-layer PCB/HDI, the protrusions withsolder material serving as electrical joints.

[0029] Then, in the example described here, the top and bottom layers51, 51′ (both produced according to FIGS. 2a-2 e) are laminated to thecore as shown in FIGS. 3a and 3 b. In this way, a 4-layer HDI build-upis formed. By doing so, the tinned copper protrusions are pressedtowards correspondingly aligned copper pads of the semifinished product21. This laminating step may be carried out at room temperature or,depending on the layer materials, at an elevated temperature. In anycase, for this laminating step, the parameters such as temperature andpressure are chosen so that the pre-tinned copper tips are soldered tothe core. If the polymer material is e.g. a Liquid Crystal Polymer(LCP), the temperature may e.g. be between 200° C. and 450° C. FIG. 3ashows the semifinished products 21, 51, 51′ and FIG. 3b depicts thelamination/soldering process. The reference numeral 61 denotes twoplates (which can be replaced by reels) between which the pressure forlaminating is developed. Because of the elevated temperature, by whichthe soldering is made possible, the base material may, depending on itscomposition, be cured simultaneously to the soldering process. As analternative to the above described procedure, protrusions without soldermaterial may be welded to the core in a hot or cold welding process. Thefour-layer build-up 71 after the lamination is shown in FIG. 3c.Finally, the outermost layers of the build-up are photo-structured in aconventional way (FIG. 3d).

[0030] The above described embodiments are by no means the only way tocarry out the invention. The expert will easily realize that numerousother embodiments can be thought of without leaving the spirit and scopeof the invention.

What is claimed is:
 1. A method for manufacturing electrical connectingelements or semifinished products comprising the steps of providing aplastically deformable dielectric substrate layer (1, 31) having a firstand a second side, the first side of said plastically deformabledielectric substrate (1, 31) layer being essentially covered by a firstconducting layer (3, 33), piercing the dielectric substrate layer (1,31), from the first side through the first conducting layer (3, 33) by aperforation tip (11) of a micro-perforation tool, so that piercing holesare formed, the piercing holes having walls which are at least partiallycovered by conductor material of said first conducting layer (3, 33) theperforation depth (d) being greater than the total thickness of thesubstrate layer (1, 31) and the first conducting layer (3, 33), andperforming a plating step, during which the first side is furtherprovided with electrically conducting material.
 2. A method according toclaim 1, wherein after piercing the substrate layer and beforeperforming the plating step, a cleaning step by plasma or wet chemicalsis performed.
 3. A method according to claim 1 or 2 wherein the secondside of the plastically deformable dielectric substrate layer (1) fromwhich one departs is at least partially covered by a second conductinglayer (5), wherein the perforation tip (11) during the piercing stepalso punctures the second conducting layer (5), and wherein the platingstep is performed until an electrical connection is formed between thefirst conducting layer (3) and the second conducting layer (5) acrossthe piercing holes, so that vias are formed.
 4. A method according toclaim 1 or 2 wherein the second side of the substrate layer (31) fromwhich one departs is free of conducing coverings, wherein theperforation depth exceeds the total thickness of the substrate layer andthe first conductor layer, and wherein after the lamination stepconductor material forms protrusions (35) on the second surface at thepierced spots.
 5. A method according to claim 3, wherein additionally asecond plastically deformable dielectric substrate layer (31) having afirst and a second side is provided, the first side of said secondplastically deformable dielectric substrate layer (31) being essentiallycovered by a conducting layer (33), the second side of said secondplastically deformable dielectric layer (31) being free of conductingcoverings, piercing the dielectric substrate layer, from the first sidethrough the first conducting layer by a perforation tip (11) of amicro-perforation tool, so that piercing holes are formed, theperforation depth (d) being greater than the total thickness of thesecond substrate layer and the conducting layer essentially covering thesecond substrate layer, performing a plating step, during which the sideof the second substrate layer which is essentially covered by aconducting layer is further provided with electrically conductingmaterial so that conductor material forms protrusions (35) on the secondsurface at the pierced spots, and joining the first and the secondsubstrate layers in a manner that the protrusions of the secondsubstrate are joined to electrically conducting material of the first orof the second conducting layer of the first substrate.
 6. A methodaccording to claim 5 wherein the protrusions (35) are provided with acap of soldering material and wherein during the joining of the firstand the second substrate layers the protrusions of the second substrateare soldered to electrically conducting material of the first or of thesecond conducting layer of the first substrate.
 7. A semifinishedproduct or an electrical connecting element manufactured using themethod according to any one of the preceding claims, comprising aninsulating layer and a first conducting layer on a first side of theinsulating layer, the first conducting layer possibly being structured,the substrate layer comprising microvias fabricated by a mechanicallyperforating the insulating layer through conductor material of the firstconducting layer and subsequent plating.